User manual

I2S Registers

www.ti.com

22.10.1.15 STMPXPER Register (Offset = 3Ch) [reset = X]

STMPXPER is shown in Figure 22-22 and described in Table 22-16.

XOSC Period Value

Figure 22-22. STMPXPER Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED VALUE

R-X R-X

Table 22-16. STMPXPER Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-0 VALUE R X

The number of 24 MHz clock cycles in the previous WCLK period

(i.e. the next value of the XOSC counter at the positive WCLK edge,

had it not been reset to 0). The value is cleared when

STMPCTL.STMP_EN = 0.

1438

Integrated Interchip Sound (I2S) Module SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback