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I2S Registers

22.10.1.10 AIFINPTR Register (Offset = 24h) [reset = X]

AIFINPTR is shown in Figure 22-17 and described in Table 22-11.

DMA Input Buffer Current Pointer

Figure 22-17. AIFINPTR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PTR

R/W-X

Table 22-11. AIFINPTR Register Field Descriptions

Bit Field Type Reset Description

31-0 PTR R/W X

Value of the DMA input buffer pointer currently used by the DMA

controller. Incremented by 1 (byte) or 2 (word) for each AHB access.

1433

SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module

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