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I2S Registers

22.10.1.8 AIFPWMVALUE Register (Offset = 1Ch) [reset = X]

AIFPWMVALUE is shown in Figure 22-15 and described in Table 22-9.

Audio Interface PWM Debug Value

Figure 22-15. AIFPWMVALUE Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED PULSE_WIDTH

R-X R/W-X

Table 22-9. AIFPWMVALUE Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-0 PULSE_WIDTH R/W X

The value written to this register determines the width of the active

high PWM pulse (pwm_debug), which starts together with MSB of

the first output word in a DMA buffer: 0x0000: Constant low 0x0001:

Width of the pulse (number of BCLK cycles, here 1). ... 0xFFFE:

Width of the pulse (number of BCLK cycles, here 65534). 0xFFFF:

Constant high

1431

SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module

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