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I2S Registers

22.10.1 I2S Registers

Table 22-1 lists the memory-mapped registers for the I2S. All register offset addresses not listed in

Table 22-1 should be considered as reserved locations and the register contents should not be modified.

Table 22-1. I2S Registers

Offset Acronym Register Name Section

0h AIFWCLKSRC WCLK Source Selection Section 22.10.1.1

4h AIFDMACFG DMA Buffer Size Configuration Section 22.10.1.2

8h AIFDIRCFG Pin Direction Section 22.10.1.3

Ch AIFFMTCFG Serial Interface Format Configuration Section 22.10.1.4

10h AIFWMASK0 Word Selection Bit Mask for Pin 0 Section 22.10.1.5

14h AIFWMASK1 Word Selection Bit Mask for Pin 1 Section 22.10.1.6

18h AIFWMASK2 Word Selection Bit Mask for Pin 2 Section 22.10.1.7

1Ch AIFPWMVALUE Audio Interface PWM Debug Value Section 22.10.1.8

20h AIFINPTRNEXT DMA Input Buffer Next Pointer Section 22.10.1.9

24h AIFINPTR DMA Input Buffer Current Pointer Section 22.10.1.10

28h AIFOUTPTRNEXT DMA Output Buffer Next Pointer Section 22.10.1.11

2Ch AIFOUTPTR DMA Output Buffer Current Pointer Section 22.10.1.12

34h STMPCTL SampleStaMP Generator Control Register Section 22.10.1.13

38h STMPXCNTCAPT0 Captured XOSC Counter Value, Capture Channel 0 Section 22.10.1.14

3Ch STMPXPER XOSC Period Value Section 22.10.1.15

40h STMPWCNTCAPT0 Captured WCLK Counter Value, Capture Channel 0 Section 22.10.1.16

44h STMPWPER WCLK Counter Period Value Section 22.10.1.17

48h STMPINTRIG WCLK Counter Trigger Value for Input Pins Section 22.10.1.18

4Ch STMPOUTTRIG WCLK Counter Trigger Value for Output Pins Section 22.10.1.19

50h STMPWSET WCLK Counter Set Operation Section 22.10.1.20

54h STMPWADD WCLK Counter Add Operation Section 22.10.1.21

58h STMPXPERMIN XOSC Minimum Period Value Section 22.10.1.22

5Ch STMPWCNT Current Value of WCNT Section 22.10.1.23

60h STMPXCNT Current Value of XCNT Section 22.10.1.24

64h STMPXCNTCAPT1 Captured XOSC Counter Value, Capture Channel 1 Section 22.10.1.25

68h STMPWCNTCAPT1 Captured WCLK Counter Value, Capture Channel 1 Section 22.10.1.26

70h IRQMASK Masked Interrupt Status Register Section 22.10.1.27

74h IRQFLAGS Raw Interrupt Status Register Section 22.10.1.28

78h IRQSET Interrupt Set Register Section 22.10.1.29

7Ch IRQCLR Interrupt Clear Register Section 22.10.1.30

1423

SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module

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