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22.7.3 Memory Buffers and Pointers
The memory access functionality operates on blocks of frames. There are separate blocks for input
samples and output samples. The number of frames per block is configured in the
[I2S:AIFDMACFG:END_FRAME_IDX] register. This is the index of the last frame in the block (that is, the
block size minus 1).
Writing a nonzero value to the [I2S:AIFDMACFG:END_FRAME_IDX] register enables and initializes the
interface.
NOTE: Before writing a nonzero value to the [I2S:AIFDMACFG:END_FRAME_IDX] register, all other
configurations must be done, and the [I2S:AIFINPTR] register and/or the [I2S:AIFOUTPTR]
register must be loaded.
The block locations in memory are determined by the [I2S:AIFINPTR] and the [I2S:AIFOUTPTR] registers.
A double-buffering scheme is used to give software time to update the pointers:
• The input memory interface uses the [I2S:AIFINPTR] register, while output memory interface uses the
[I2S:AIFOUTPTR] register.
• Software must write the next block addresses to the [I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT]
registers.
• When loading and storing samples, the [I2S:AIFINPTR] and [I2S:AIFOUTPTR] registers increase for
each memory access.
• When a block is finished, the following occurs:
– Input memory interface block:
• [I2S:AIFINPTR] = [I2S:AIFINPTRNEXT]
• [I2S:AIFINPTRNEXT] = NULL
• [I2S:IRQ_FLAGS:AIF_DMA_IN] is set.
– Output memory interface block:
• [I2S:AIFOUTPTR] = [I2S:AIFOUTPTRNEXT]
• [I2S:AIFOUTPTRNEXT] = NULL
• [I2S:IRQ_FLAGS:AIF_DMA_OUT] is set.
The interrupt, or alternatively the [I2S:AIFINPTRNEXT] and [I2S:AIFOUTPTRNEXT] registers returning to
NULL, signals software to write the next pointers. Failing to write the next pointers to the
[I2S:AIFINPTRNEXT] and/or [I2S:AIFOUTPTRNEXT] registers before the running block finishes asserts
the [I2S:IRQFLAGS.PTR_ERR] register.
22.8 Samplestamp Generator
The samplestamp generator is mainly used to control the I/O streams of the I2S module. It also provides a
way to synchronize I2S modules over wireless networks to achieve correct and fixed audio latency.
The samplestamp generator is enabled and is running when [I2S:STMPCTL:STMP_EN] = 1. When the
[I2S:STMPCTL:STMP_EN] register goes from 1 to 0, all internal counters and capture values are reset.
Because the samplestamp generator controls I/O streaming; it must always be enabled.
1418
Integrated Interchip Sound (I2S) Module SWCU117A–February 2015–Revised March 2015
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