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WCLK
BCLK
ADx
MSB MSB
LSB
LSB
Right channel
Left channel
WCLK period = 1/F
S
n-1 n-2
n-3
0
n-1 n-2 n-3
2
1 0
2 1 n-1
WCLK
ADx
BCLK
0
3
21 1
0
Left channel
MSB LSB MSB
Right channel
WCLK period = 1/Fs
3
2n-1
n-3
1
0
LSB
n-2n-1
n-3
n-2
www.ti.com Serial Interface Formats
Figure 22-4. I2S Interface Format
22.6.2 Left Justified (LJF)
LJF is a dual-phase format, [I2S:AIFFMTCFG:DUAL_PHASE] = 1, with a 50% WCLK duty cycle and MSB
of each sample word aligned with the edge of WCLK ; that is, [I2S:AIFFMTCFG:DATA_DELAY] = 0. For
any given sample, the left channel is transferred first when WCLK is high, and the right channel is
transferred second when WCLK is low. Data is sampled on the rising edge of BCLK and updated on the
falling edge of BCLK, [I2S: AIFFMTCFG:SMPL_EDGE] = 1.
The maximum number of bits per word is specified using the [I2S: AIFFMTCFG: WORD_LEN] register.
The number of BCLK cycles in a phase must be equal to or higher than this number. When there is an
IDLE period at the end of the clock phase, MSB of the next sample is output during this interval.
Figure 22-5. LJF Interface Format
22.6.3 Right Justified (RJF)
RJF is a dual-phase format, [I2S:AIFFMTCFG:DUAL_PHASE] = 1, with a 50% WCLK duty cycle and LSB
of each sample word aligned with the edge of WCLK. For any given sample, the left channel is transferred
first when WCLK is high, and the right channel is transferred second when WCLK is low. Data is sampled
on the rising edge of BCLK and updated on the falling edge of BCLK,
[I2S: AIFFMTCFG:SMPL_EDGE] = 1.
There is an optional IDLE period at the start of the clock phase specified by the
[I2S:AIFFMTCFG:DATA_DELAY] register; logical 0 is output during this DATA DELAY interval.
The maximum number of bits per word is specified using the [I2S:AIFFMTCFG: WORD_LEN] register.
The number of BCLK cycles in each phase must be equal to [I2S: AIFFMTCFG: WORD_LEN] +
[I2S:AIFFMTCFG:DATA_DELAY].
1415
SWCU117A–February 2015–Revised March 2015 Integrated Interchip Sound (I2S) Module
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