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www.ti.com Cortex-M3 Processor Registers
2.7.4.9 NVIC_ICER0 Register (Offset = 180h) [reset = X]
NVIC_ICER0 is shown in Figure 2-79 and described in Table 2-105.
Irq 0 to 31 Clear Enable This register is used to disable interrupts and determine which interrupts are
currently enabled.
Figure 2-79. NVIC_ICER0 Register
31 30 29 28 27 26 25 24
CLRENA31 CLRENA30 CLRENA29 CLRENA28 CLRENA27 CLRENA26 CLRENA25 CLRENA24
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
CLRENA23 CLRENA22 CLRENA21 CLRENA20 CLRENA19 CLRENA18 CLRENA17 CLRENA16
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
CLRENA15 CLRENA14 CLRENA13 CLRENA12 CLRENA11 CLRENA10 CLRENA9 CLRENA8
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
CLRENA7 CLRENA6 CLRENA5 CLRENA4 CLRENA3 CLRENA2 CLRENA1 CLRENA0
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 2-105. NVIC_ICER0 Register Field Descriptions
Bit Field Type Reset Description
31 CLRENA31 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.
30 CLRENA30 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.
29 CLRENA29 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.
28 CLRENA28 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.
27 CLRENA27 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.
26 CLRENA26 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.
25 CLRENA25 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.
24 CLRENA24 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.
23 CLRENA23 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.
22 CLRENA22 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.
21 CLRENA21 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit disables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.
141
SWCU117A–February 2015–Revised March 2015
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