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C Registers
21.5.1.17 MICR Register (Offset = 81Ch) [reset = X]
MICR is shown in Figure 21-30 and described in Table 21-19.
Master Interrupt Clear This register clears the raw and masked interrupt.
Figure 21-30. MICR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IC
W-X W-X
Table 21-19. MICR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 IC W X
Interrupt clear Writing 1 to this bit clears MRIS.RIS and MMIS.MIS .
Reading this register returns no meaningful data.
1409
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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