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21.5.1.14 MIMR Register (Offset = 810h) [reset = X]
MIMR is shown in Figure 21-27 and described in Table 21-16.
Master Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 21-27. MIMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED IM
R-X R/W-X
Table 21-16. MIMR Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 IM R/W X
Interrupt mask 0: The MRIS.RIS interrupt is suppressed and not sent
to the interrupt controller. 1: The master interrupt is sent to the
interrupt controller when the MRIS.RIS is set.
0h = Disable Interrupt
1h = Enable Interrupt
1406
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
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