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C Registers
21.5.1.13 MTPR Register (Offset = 80Ch) [reset = X]
MTPR is shown in Figure 21-26 and described in Table 21-15.
I2C Master Timer Period This register specifies the period of the SCL clock.
Figure 21-26. MTPR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
TPR_7 TPR
R/W-X R/W-1h
Table 21-15. MTPR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
7 TPR_7 R/W X
Must be set to 0 to set TPR. If set to 1, a write to TPR will be
ignored.
6-0 TPR R/W 1h
SCL clock period This field specifies the period of the SCL clock.
SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD where:
SCL_PRD is the SCL line period (I2C clock). TPR is the timer period
register value (range of 1 to 127) SCL_LP is the SCL low period
(fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is
the system clock period in ns.
1405
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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