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21.5.1.10 MSTAT Register (Offset = 804h) [reset = X]
MSTAT is shown in Figure 21-23 and described in Table 21-12.
Master Status
Figure 21-23. MSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED BUSBSY IDLE ARBLST DATACK_N ADRACK_N ERR BUSY
R-X R-X R-1h R-X R-X R-X R-X R-X
Table 21-12. MSTAT Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
6 BUSBSY R X
Bus busy 0: The I2C bus is idle. 1: The I2C bus is busy. The bit
changes based on the MCTRL.START and MCTRL.STOP
conditions.
5 IDLE R 1h
I2C idle 0: The I2C controller is not idle. 1: The I2C controller is idle.
4 ARBLST R X
Arbitration lost 0: The I2C controller won arbitration. 1: The I2C
controller lost arbitration.
3 DATACK_N R X
Data Was Not Acknowledge 0: The transmitted data was
acknowledged. 1: The transmitted data was not acknowledged.
2 ADRACK_N R X
Address Was Not Acknowledge 0: The transmitted address was
acknowledged. 1: The transmitted address was not acknowledged.
1 ERR R X
Error 0: No error was detected on the last operation. 1: An error
occurred on the last operation.
0 BUSY R X
I2C busy 0: The controller is idle. 1: The controller is busy. When this
bit-field is set, the other status bits are not valid. Note: The I2C
controller requires four SYSBUS clock cycles to assert the BUSY
status after I2C master operation has been initiated through MCTRL
register. Hence after programming MCTRL register, application is
requested to wait for four SYSBUS clock cycles before issuing a
controller status inquiry through MSTAT register. Any prior inquiry
would result in wrong status being reported.
1402
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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