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C Registers

21.5.1.9 MSA Register (Offset = 800h) [reset = X]

MSA is shown in Figure 21-22 and described in Table 21-11.

Master Salve Address This register contains seven address bits of the slave to be accessed by the master

(a6-a0), and an RS bit determining if the next operation is a receive or transmit.

Figure 21-22. MSA Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED SA RS

R-X R/W-X R/W-X

Table 21-11. MSA Register Field Descriptions

Bit Field Type Reset Description

31-8 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

7-1 SA R/W X

I2C master slave address Defines which slave is addressed for the

transaction in master mode

0 RS R/W X

Receive or Send This bit-field specifies if the next operation is a

receive (high) or a transmit/send (low) from the addressed slave SA.

0h = Transmit/send data to slave

1h = Receive data from slave

1401

SWCU117A–February 2015–Revised March 2015

Inter-Integrated Circuit (I

C) Interface

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