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I
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21.5.1.8 SICR Register (Offset = 18h) [reset = X]
SICR is shown in Figure 21-21 and described in Table 21-10.
Slave Interrupt Clear This register clears the raw interrupt SRIS.
Figure 21-21. SICR Register
31 30 29 28 27 26 25 24
RESERVED
W-X
23 22 21 20 19 18 17 16
RESERVED
W-X
15 14 13 12 11 10 9 8
RESERVED
W-X
7 6 5 4 3 2 1 0
RESERVED STOPIC STARTIC DATAIC
W-X W-X W-X W-X
Table 21-10. SICR Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 STOPIC W X
Stop condition interrupt clear Writing 1 to this bit clears
SRIS.STOPRIS and SMIS.STOPMIS.
1 STARTIC W X
Start condition interrupt clear Writing 1 to this bit clears
SRIS.STARTRIS SMIS.STARTMIS.
0 DATAIC W X
Data interrupt clear Writing 1 to this bit clears SRIS.DATARIS
SMIS.DATAMIS.
1400
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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