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21.5.1.6 SRIS Register (Offset = 10h) [reset = X]
SRIS is shown in Figure 21-19 and described in Table 21-8.
Slave Raw Interrupt Status This register shows the unmasked interrupt status.
Figure 21-19. SRIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED STOPRIS STARTRIS DATARIS
R-X R-X R-X R-X
Table 21-8. SRIS Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 STOPRIS R X
Stop condition raw interrupt status 0: No interrupt 1: A Stop condition
interrupt is pending. This bit is cleared by writing a 1 to
SICR.STOPIC.
1 STARTRIS R X
Start condition raw interrupt status 0: No interrupt 1: A Start
condition interrupt is pending. This bit is cleared by writing a 1 to
SICR.STARTIC.
0 DATARIS R X
Data raw interrupt status 0: No interrupt 1: A data received or data
requested interrupt is pending. This bit is cleared by writing a 1 to
the SICR.DATAIC.
1398
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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