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C Registers
21.5.1.5 SIMR Register (Offset = Ch) [reset = X]
SIMR is shown in Figure 21-18 and described in Table 21-7.
Slave Interrupt Mask This register controls whether a raw interrupt is promoted to a controller interrupt.
Figure 21-18. SIMR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED STOPIM STARTIM DATAIM
R-X R/W-X R/W-X R/W-X
Table 21-7. SIMR Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 STOPIM R/W X
Stop condition interrupt mask 0: The SRIS.STOPRIS interrupt is
suppressed and not sent to the interrupt controller. 1: The
SRIS.STOPRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt
1 STARTIM R/W X
Start condition interrupt mask 0: The SRIS.STARTRIS interrupt is
suppressed and not sent to the interrupt controller. 1: The
SRIS.STARTRIS interrupt is enabled and sent to the interrupt
controller.
0h = Disable Interrupt
1h = Enable Interrupt
0 DATAIM R/W X
Data interrupt mask 0: The SRIS.DATARIS interrupt is suppressed
and not sent to the interrupt controller. 1: The SRIS.DATARIS
interrupt is enabled and sent to the interrupt controller.
1397
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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