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2
C Registers
21.5.1.3 SCTL Register (Offset = 4h) [reset = X]
SCTL is shown in Figure 21-16 and described in Table 21-5.
Slave Control Note: This register shares address with SSTAT, meaning that this register functions as a
control register when written, and a status register when read.
Figure 21-16. SCTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
W-X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DA
W-X W-X
Table 21-5. SCTL Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED W X
Software should not rely on the value of a reserved field. Writing any
other value may result in undefined behavior.
0 DA W X
Device active 0: Disables the I2C slave operation 1: Enables the I2C
slave operation
1395
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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