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I
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21.5.1.2 SSTAT Register (Offset = 4h) [reset = X]
SSTAT is shown in Figure 21-15 and described in Table 21-4.
Slave Status Internal Note: This register shares address with SCTL, meaning that this register functions
as a control register when written, and a status register when read.
Figure 21-15. SSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED FBR TREQ RREQ
R-X R-X R-X R-X
Table 21-4. SSTAT Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 FBR R X
First byte received 0: The first byte has not been received. 1: The
first byte following the slave's own address has been received. This
bit is only valid when the RREQ bit is set and is automatically
cleared when data has been read from the SDR register. Note: This
bit is not used for slave transmit operations.
1 TREQ R X
Transmit request 0: No outstanding transmit request. 1: The I2C
controller has been addressed as a slave transmitter and is using
clock stretching to delay the master until data has been written to the
SDR register.
0 RREQ R X
Receive request 0: No outstanding receive data 1: The I2C controller
has outstanding receive data from the I2C master and is using clock
stretching to delay the master until data has been read from the SDR
register.
1394
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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