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2
C Registers
21.5.1.1 SOAR Register (Offset = 0h) [reset = X]
SOAR is shown in Figure 21-14 and described in Table 21-3.
Slave Own Address This register consists of seven address bits that identify this I2C device on the I2C
bus.
Figure 21-14. SOAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED OAR
R-X R/W-X
Table 21-3. SOAR Register Field Descriptions
Bit Field Type Reset Description
31-7 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
6-0 OAR R/W X
I2C slave own address This field specifies bits a6 through a0 of the
slave address.
1393
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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