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C Registers

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21.5.1 I2C Registers

Table 21-2 lists the memory-mapped registers for the I2C. All register offset addresses not listed in

Table 21-2 should be considered as reserved locations and the register contents should not be modified.

Table 21-2. I2C Registers

Offset Acronym Register Name Section

0h SOAR Slave Own Address Section 21.5.1.1

4h SSTAT Slave Status Section 21.5.1.2

4h SCTL Slave Control Section 21.5.1.3

8h SDR Slave Data Section 21.5.1.4

Ch SIMR Slave Interrupt Mask Section 21.5.1.5

10h SRIS Slave Raw Interrupt Status Section 21.5.1.6

14h SMIS Slave Masked Interrupt Status Section 21.5.1.7

18h SICR Slave Interrupt Clear Section 21.5.1.8

800h MSA Master Salve Address Section 21.5.1.9

804h MSTAT Master Status Section 21.5.1.10

804h MCTRL Master Control Section 21.5.1.11

808h MDR Master Data Section 21.5.1.12

80Ch MTPR I2C Master Timer Period Section 21.5.1.13

810h MIMR Master Interrupt Mask Section 21.5.1.14

814h MRIS Master Raw Interrupt Status Section 21.5.1.15

818h MMIS Master Masked Interrupt Status Section 21.5.1.16

81Ch MICR Master Interrupt Clear Section 21.5.1.17

820h MCR Master Configuration Section 21.5.1.18

1392

SWCU117A–February 2015–Revised March 2015

Inter-Integrated Circuit (I

C) Interface

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