User manual

Idle
Write slave address
to I2C_MSA
Read I2C_MSTAT
Read I2C_MSTAT
BUSY bit = 0?
BUSY bit = 0?
ERR bit = 0?Idle
Error service
No
Yes
No
Yes
No
Sequence may be
omitted in a single
master system.
Write 0 ±1011 to
I2C_MCTRL
ERR bit = 0?
Index = m - 1?
ARBLST bit = 1?
Idle
BUSY bit = 0?
Write 0 ± 1001 to
I2C_MCTRL
Write 0 ± 101 to
I2C_MCTRL
Read I2C_MSTAT
Read data from
I2C_MDR
Error serivce
Write 0 ± 100 to
I2C_MCTRL
No
No
Yes
Yes
Yes
No
Read data from
I2C_MDR
NoYes
Yes
www.ti.com Functional Description
Figure 21-10. Master RECEIVE With Repeated Start Condition
1387
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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