User manual

Idle
Write slave
address to
I2C_MSA
Read I2C_MSTAT
Read I2C_MSTAT
Write 0 t 111 to
I2C_MCTRL
BUSY bit = 0?
BUSY bit = 0? ERR bit = 0?
Idle
Error service
Yes
No
Yes
No
Yes
No
Sequence may be omitted in
a single master system.
Read data from
I2C_MDR
www.ti.com Functional Description
Figure 21-8. Master Single RECEIVE
1385
SWCU117A–February 2015–Revised March 2015
Inter-Integrated Circuit (I
2
C) Interface
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