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SSI Registers

20.7.1.10 DMACR Register (Offset = 24h) [reset = X]

DMACR is shown in Figure 20-22 and described in Table 20-12.

DMA Control

Figure 20-22. DMACR Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED TXDMAE RXDMAE

R-X R/W-X R/W-X

Table 20-12. DMACR Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 TXDMAE R/W X

Transmit DMA enable. If this bit is set to 1, DMA for the transmit

FIFO is enabled.

0 RXDMAE R/W X

Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO

is enabled.

1377

SWCU117A–February 2015–Revised March 2015 Synchronous Serial Interface (SSI)

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