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SSI Registers

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20.7.1.9 ICR Register (Offset = 20h) [reset = X]

ICR is shown in Figure 20-21 and described in Table 20-11.

Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.

Figure 20-21. ICR Register

31 30 29 28 27 26 25 24

RESERVED

W-X

23 22 21 20 19 18 17 16

RESERVED

W-X

15 14 13 12 11 10 9 8

RESERVED

W-X

7 6 5 4 3 2 1 0

RESERVED RTIC RORIC

W-X W-X W-X

Table 20-11. ICR Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 RTIC W X

Clear the receive timeout interrupt: Writing 1 to this field clears the

timeout interrupt (RIS.RTRIS). Writing 0 has no effect.

0 RORIC W X

Clear the receive overrun interrupt: Writing 1 to this field clears the

overrun error interrupt (RIS.RORRIS). Writing 0 has no effect.

1376

Synchronous Serial Interface (SSI) SWCU117A–February 2015–Revised March 2015

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