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20.7.1.6 IMSC Register (Offset = 14h) [reset = X]
IMSC is shown in Figure 20-18 and described in Table 20-8.
Interrupt Mask Set and Clear
Figure 20-18. IMSC Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED TXIM RXIM RTIM RORIM
R-X R/W-X R/W-X R/W-X R/W-X
Table 20-8. IMSC Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3 TXIM R/W X
Transmit FIFO interrupt mask: A read returns the current mask for
transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO
interrupt is set which means the interrupt state will be reflected in
MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS
will not reflect the interrupt.
2 RXIM R/W X
Receive FIFO interrupt mask: A read returns the current mask for
receive FIFO interrupt. On a write of 1, the mask for receive FIFO
interrupt is set which means the interrupt state will be reflected in
MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS
will not reflect the interrupt.
1 RTIM R/W X
Receive timeout interrupt mask: A read returns the current mask for
receive timeout interrupt. On a write of 1, the mask for receive
timeout interrupt is set which means the interrupt state will be
reflected in MIS.RTMIS. A write of 0 clears the mask which means
MIS.RTMIS will not reflect the interrupt.
0 RORIM R/W X
Receive overrun interrupt mask: A read returns the current mask for
receive overrun interrupt. On a write of 1, the mask for receive
overrun interrupt is set which means the interrupt state will be
reflected in MIS.RORMIS. A write of 0 clears the mask which means
MIS.RORMIS will not reflect the interrupt.
1373
SWCU117A–February 2015–Revised March 2015 Synchronous Serial Interface (SSI)
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