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www.ti.com Cortex-M3 Processor Registers
2.7.4.7 NVIC_ISER0 Register (Offset = 100h) [reset = X]
NVIC_ISER0 is shown in Figure 2-77 and described in Table 2-103.
Irq 0 to 31 Set Enable This register is used to enable interrupts and determine which interrupts are
currently enabled.
Figure 2-77. NVIC_ISER0 Register
31 30 29 28 27 26 25 24
SETENA31 SETENA30 SETENA29 SETENA28 SETENA27 SETENA26 SETENA25 SETENA24
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
SETENA23 SETENA22 SETENA21 SETENA20 SETENA19 SETENA18 SETENA17 SETENA16
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
SETENA15 SETENA14 SETENA13 SETENA12 SETENA11 SETENA10 SETENA9 SETENA8
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
SETENA7 SETENA6 SETENA5 SETENA4 SETENA3 SETENA2 SETENA1 SETENA0
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 2-103. NVIC_ISER0 Register Field Descriptions
Bit Field Type Reset Description
31 SETENA31 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details).
Reading the bit returns its current enable state.
30 SETENA30 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details).
Reading the bit returns its current enable state.
29 SETENA29 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details).
Reading the bit returns its current enable state.
28 SETENA28 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details).
Reading the bit returns its current enable state.
27 SETENA27 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details).
Reading the bit returns its current enable state.
26 SETENA26 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details).
Reading the bit returns its current enable state.
25 SETENA25 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details).
Reading the bit returns its current enable state.
24 SETENA24 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details).
Reading the bit returns its current enable state.
23 SETENA23 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details).
Reading the bit returns its current enable state.
22 SETENA22 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details).
Reading the bit returns its current enable state.
21 SETENA21 R/W X
Writing 0 to this bit has no effect, writing 1 to this bit enables the
interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details).
Reading the bit returns its current enable state.
137
SWCU117A–February 2015–Revised March 2015
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