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SSI Registers

20.7.1 SSI Registers

Table 20-2 lists the memory-mapped registers for the SSI. All register offset addresses not listed in

Table 20-2 should be considered as reserved locations and the register contents should not be modified.

Table 20-2. SSI Registers

Offset Acronym Register Name Section

0h CR0 Control 0 Section 20.7.1.1

4h CR1 Control 1 Section 20.7.1.2

8h DR Data Section 20.7.1.3

Ch SR Status Section 20.7.1.4

10h CPSR Clock Prescale Section 20.7.1.5

14h IMSC Interrupt Mask Set and Clear Section 20.7.1.6

18h RIS Raw Interrupt Status Section 20.7.1.7

1Ch MIS Masked Interrupt Status Section 20.7.1.8

20h ICR Interrupt Clear Section 20.7.1.9

24h DMACR DMA Control Section 20.7.1.10

1367

SWCU117A–February 2015–Revised March 2015 Synchronous Serial Interface (SSI)

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