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2.7.4.6 STCR Register (Offset = 1Ch) [reset = X]
STCR is shown in Figure 2-76 and described in Table 2-102.
SysTick Calibration Value Used to enable software to scale to any required speed using divide and
multiply.
Figure 2-76. STCR Register
31 30 29 28 27 26 25 24
NOREF SKEW RESERVED
R-1h R-1h R-X
23 22 21 20 19 18 17 16
TENMS
R-75300h
15 14 13 12 11 10 9 8
TENMS
R-75300h
7 6 5 4 3 2 1 0
TENMS
R-75300h
Table 2-102. STCR Register Field Descriptions
Bit Field Type Reset Description
31 NOREF R 1h
Reads as one. Indicates that no separate reference clock is
provided.
30 SKEW R 1h
Reads as one. The calibration value is not exactly 10ms because of
clock frequency. This could affect its suitability as a software real
time clock.
29-24 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
23-0 TENMS R 75300h
An optional Reload value to be used for 10ms (100Hz) timing,
subject to system clock skew errors. The value read is valid only
when core clock is at 48MHz.
136
SWCU117A–February 2015–Revised March 2015
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