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Synchronous Serial Interface

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20.1 Synchronous Serial Interface

The two SSI modules of CC26xx have the following features:

• Programmable interface operation for Motorola SPI, MICROWIRE, or TI SSIs

• Configurable as a master or a slave on the interface

• Programmable clock bit rate and prescaler

• Separate transmit (TX) and receive (RX) first-in first-out buffers (FIFOs), each 16 bits wide and 8

locations deep

• Programmable data frame size from 4 to 16 bits

• Internal loopback test mode for diagnostic and debug testing

• Interrupts for transmit and receive FIFOs, overrun and time-out interrupts, and DMA done interrupts

• Efficient transfers using micro direct memory access controller (μDMA):

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO

contains four or more entries

– Transmit single request asserted when there is space in the FIFO; burst request asserted when

FIFO contains four or fewer entries

1354

Synchronous Serial Interface (SSI) SWCU117A–February 2015–Revised March 2015

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