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19.7.1.13 ICR Register (Offset = 44h) [reset = 0h]
ICR is shown in Figure 19-16 and described in Table 19-16.
Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
Figure 19-16. ICR Register
31 30 29 28 27 26 25 24
RESERVED
W-0h
23 22 21 20 19 18 17 16
RESERVED
W-0h
15 14 13 12 11 10 9 8
RESERVED OEIC BEIC PEIC
W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
FEIC RTIC TXIC RXIC RESERVED CTSMIC RESERVED
W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 19-16. ICR Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED W 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
10 OEIC W 0h
Overrun error interrupt clear: Writing 1 to this field clears the overrun
error interrupt (RIS.OERIS). Writing 0 has no effect.
9 BEIC W 0h
Break error interrupt clear: Writing 1 to this field clears the break
error interrupt (RIS.BERIS). Writing 0 has no effect.
8 PEIC W 0h
Parity error interrupt clear: Writing 1 to this field clears the parity
error interrupt (RIS.PERIS). Writing 0 has no effect.
7 FEIC W 0h
Framing error interrupt clear: Writing 1 to this field clears the framing
error interrupt (RIS.FERIS). Writing 0 has no effect.
6 RTIC W 0h
Receive timeout interrupt clear: Writing 1 to this field clears the
receive timeout interrupt (RIS.RTRIS). Writing 0 has no effect.
5 TXIC W 0h
Transmit interrupt clear: Writing 1 to this field clears the transmit
interrupt (RIS.TXRIS). Writing 0 has no effect.
4 RXIC W 0h
Receive interrupt clear: Writing 1 to this field clears the receive
interrupt (RIS.RXRIS). Writing 0 has no effect.
3-2 RESERVED W 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Write 0
1 CTSMIC W 0h
Clear to Send (CTS) modem interrupt clear: Writing 1 to this field
clears the clear to send interrupt (RIS.CTSRMIS). Writing 0 has no
effect.
0 RESERVED W 0h
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
Write 0.
1351
SWCU117A–February 2015–Revised March 2015 Universal Asynchronous Receivers and Transmitters (UARTS)
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