User manual

UARTS Registers www.ti.com
19.7.1.12 MIS Register (Offset = 40h) [reset = X]
MIS is shown in Figure 19-15 and described in Table 19-15.
Masked Interrupt Status
Figure 19-15. MIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED OEMIS BEMIS PEMIS
R-X R-X R-X R-X
7 6 5 4 3 2 1 0
FEMIS RTMIS TXMIS RXMIS RESERVED CTSMMIS RESERVED
R-X R-X R-X R-X R-X R-X R-X
Table 19-15. MIS Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
10 OEMIS R X
Overrun error masked interrupt status: This field returns the masked
interrupt state of the overrun interrupt which is the AND product of
raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM.
9 BEMIS R X
Break error masked interrupt status: This field returns the masked
interrupt state of the break error interrupt which is the AND product
of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM.
8 PEMIS R X
Parity error masked interrupt status: This field returns the masked
interrupt state of the parity error interrupt which is the AND product
of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM.
7 FEMIS R X
Framing error masked interrupt status: Returns the masked interrupt
state of the framing error interrupt which is the AND product of raw
interrupt state RIS.FERIS and the mask setting IMSC.FEIM.
6 RTMIS R X
Receive timeout masked interrupt status: Returns the masked
interrupt state of the receive timeout interrupt. The raw interrupt for
receive timeout cannot be set unless the mask is set (IMSC.RTIM =
1). This is because the mask acts as an enable for power saving.
That is, the same status can be read from RTMIS and RIS.RTRIS.
5 TXMIS R X
Transmit masked interrupt status: This field returns the masked
interrupt state of the transmit interrupt which is the AND product of
raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM.
4 RXMIS R X
Receive masked interrupt status: This field returns the masked
interrupt state of the receive interrupt which is the AND product of
raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM.
3-2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 CTSMMIS R X
Clear to Send (CTS) modem masked interrupt status: This field
returns the masked interrupt state of the clear to send interrupt
which is the AND product of raw interrupt state RIS.CTSRMIS and
the mask setting IMSC.CTSMIM.
0 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1350
Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated