User manual

www.ti.com

UARTS Registers

Table 19-13. IMSC Register Field Descriptions (continued)

Bit Field Type Reset Description

4 RXIM R/W X

Receive interrupt mask. A read returns the current mask for UART's

receive interrupt. On a write of 1, the mask of the overrun error

interrupt is set which means the interrupt state will be reflected in

MIS.RXMIS. A write of 0 clears the mask which means MIS.RXMIS

will not reflect the interrupt.

3-2 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 CTSMIM R/W X

Clear to Send (CTS) modem interrupt mask. A read returns the

current mask for UART 's clear to send interrupt. On a write of 1, the

mask of the overrun error interrupt is set which means the interrupt

state will be reflected in MIS.CTSMMIS. A write of 0 clears the mask

which means MIS.CTSMMIS will not reflect the interrupt.

0 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1347

SWCU117A–February 2015–Revised March 2015 Universal Asynchronous Receivers and Transmitters (UARTS)

Submit Documentation Feedback