User manual

UARTS Registers www.ti.com
19.7.1.10 IMSC Register (Offset = 38h) [reset = X]
IMSC is shown in Figure 19-13 and described in Table 19-13.
Interrupt Mask Set/Clear
Figure 19-13. IMSC Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED OEIM BEIM PEIM
R/W-X R/W-X R/W-X R/W-X
7 6 5 4 3 2 1 0
FEIM RTIM TXIM RXIM RESERVED CTSMIM RESERVED
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Table 19-13. IMSC Register Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
10 OEIM R/W X
Overrun error interrupt mask. A read returns the current mask for
UART's overrun error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.OEMIS. A write of 0 clears the mask which means
MIS.OEMIS will not reflect the interrupt.
9 BEIM R/W X
Break error interrupt mask. A read returns the current mask for
UART's break error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.BEMIS. A write of 0 clears the mask which means
MIS.BEMIS will not reflect the interrupt.
8 PEIM R/W X
Parity error interrupt mask. A read returns the current mask for
UART's parity error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.PEMIS. A write of 0 clears the mask which means
MIS.PEMIS will not reflect the interrupt.
7 FEIM R/W X
Framing error interrupt mask. A read returns the current mask for
UART's framing error interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.FEMIS. A write of 0 clears the mask which means
MIS.FEMIS will not reflect the interrupt.
6 RTIM R/W X
Receive timeout interrupt mask. A read returns the current mask for
UART's receive timeout interrupt. On a write of 1, the mask of the
overrun error interrupt is set which means the interrupt state will be
reflected in MIS.RTMIS. A write of 0 clears the mask which means
this bitfield will not reflect the interrupt. The raw interrupt for receive
timeout RIS.RTRIS cannot be set unless the mask is set (RTIM = 1).
This is because the mask acts as an enable for power saving. That
is, the same status can be read from MIS.RTMIS and RIS.RTRIS.
5 TXIM R/W X
Transmit interrupt mask. A read returns the current mask for UART's
transmit interrupt. On a write of 1, the mask of the overrun error
interrupt is set which means the interrupt state will be reflected in
MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS
will not reflect the interrupt.
1346
Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated