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19.7.1.8 CTL Register (Offset = 30h) [reset = X]
CTL is shown in Figure 19-11 and described in Table 19-11.
Control
Figure 19-11. CTL Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
CTSEN RTSEN RESERVED RTS RESERVED RXE TXE
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-1h R/W-1h
7 6 5 4 3 2 1 0
LBE RESERVED UARTEN
R/W-X R/W-X R/W-X
Table 19-11. CTL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
15 CTSEN R/W X
CTS hardware flow control enable
0h = CTS hardware flow control disabled
1h = CTS hardware flow control enabled
14 RTSEN R/W X
RTS hardware flow control enable
0h = RTS hardware flow control disabled
1h = RTS hardware flow control enabled
13-12 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
11 RTS R/W X
Request to Send This bit is the complement of the active-low UART
RTS output. That is, when the bit is programmed to a 1 then RTS
output on the pins is LOW.
10 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
9 RXE R/W 1h
UART Receive Enable If the UART is disabled in the middle of
reception, it completes the current character before stopping.
0h = UART Receive disabled
1h = UART Receive enabled
8 TXE R/W 1h
UART Transmit Enable If the UART is disabled in the middle of
transmission, it completes the current character before stopping.
0h = UART Transmit disabled
1h = UART Transmit enabled
7 LBE R/W X
UART Loop Back Enable: Enabling the loop-back mode connects
the UARTTXD output from the UART to UARTRXD input of the
UART.
0h = Loop Back disabled
1h = Loop Back enabled
6-1 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 UARTEN R/W X
UART Enable
0h = UART disabled
1h = UART enabled
1344
Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015
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