User manual

UARTS Registers

www.ti.com

19.7.1.6 FBRD Register (Offset = 28h) [reset = X]

FBRD is shown in Figure 19-9 and described in Table 19-9.

Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the

baudrate will not be updated until transmission or reception of the current character is complete.

Figure 19-9. FBRD Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED DIVFRAC

R/W-X R/W-X

Table 19-9. FBRD Register Field Descriptions

Bit Field Type Reset Description

31-6 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

5-0 DIVFRAC R/W X

Fractional Baud-Rate Divisor: The baud rate divisor is calculated

using the formula below: Baud rate divisor = (UART reference clock

frequency) / (16 * Baud rate) Baud rate divisor must be minimum 1

and maximum 65535. That is, IBRD.DIVINT=0 does not give a valid

baud rate. Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in

DIVFRAC will be illegal. A valid value must be written to this field

before the UART can be used for RX or TX operations.

1342

Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback