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UARTS Registers

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19.7.1 UART Registers

Table 19-3 lists the memory-mapped registers for the UART. All register offset addresses not listed in

Table 19-3 should be considered as reserved locations and the register contents should not be modified.

Table 19-3. UART Registers

Offset Acronym Register Name Section

0h DR Data Section 19.7.1.1

4h RSR Status Section 19.7.1.2

4h ECR Error Clear Section 19.7.1.3

18h FR Flag Section 19.7.1.4

24h IBRD Integer Baud-Rate Divisor Section 19.7.1.5

28h FBRD Fractional Baud-Rate Divisor Section 19.7.1.6

2Ch LCRH Line Control Section 19.7.1.7

30h CTL Control Section 19.7.1.8

34h IFLS Interrupt FIFO Level Select Section 19.7.1.9

38h IMSC Interrupt Mask Set/Clear Section 19.7.1.10

3Ch RIS Raw Interrupt Status Section 19.7.1.11

40h MIS Masked Interrupt Status Section 19.7.1.12

44h ICR Interrupt Clear Section 19.7.1.13

48h DMACTL DMA Control Section 19.7.1.14

1336

Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015

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