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Functional Description

• TX: The transmit interrupt changes state when one of the following events occurs:

– If the FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger

level, then the transmit interrupt is asserted high. The transmit interrupt is cleared by writing data to

the transmit FIFO until it becomes greater than the trigger level, or by clearing the interrupt.

– If the FIFOs are disabled (have a depth of one location) and there is no data present in the

transmitters single location, the transmit interrupt is asserted high. The interrupt is cleared by

performing a single write to the transmit FIFO, or by clearing the interrupt.

• RX time-out: The receive time-out interrupt is asserted when the receive FIFO is not empty, and no

more data is received during a 32-bit period. The receive time-out interrupt is cleared either when the

FIFO becomes empty through reading all the data (or by reading the holding register), or when 1 is

written to the corresponding bit of the interrupt clear register [UART_ICR].

• Modem status: The modem status interrupt is asserted if the modem status signal uart_cts changes. It

can be cleared using the corresponding clear bit in the [UART_ICR] register.

• Error: The error interrupt is asserted when an error occurs in the reception of data by the UART. The

interrupt can be caused by a number of different error conditions: framing, parity, break, or overrun.

The cause of the interrupt can be determined by reading the [UART_RIS] register or the [UART_MIS]

In addition to the five events produced by the UART module, two additional events are ORed to the

interrupt line:

• RX DMA done: Indicates that the receiver DMA has completed its task. This is a level interrupt

provided by the DMA module, and is cleared using the dma_done clear register in DMA module.

• TX DMA done: Indicates that the transmit DMA has completed its task. This is a level interrupt

provided by the DMA module, and is cleared using the dma_done clear register in DMA module.

19.4.7 Loopback Operation

The UART can be placed into an internal loopback mode for diagnostic or debug work by setting the LBE

bit in the [UART_CTL] register. In loopback mode, data transmitted on the UARTTXD output is received

on the UARTRXD input. The LBE bit should be set before the UART is enabled.

19.5 Interface to DMA

The CC26xx device provides an interface to connect to a DMA controller. Figure 19-3 shows the interface

between the DMA and UART. This interface contains four DMA requests as outputs (RX Single, RX Burst,

TX Single, and TX Burst). The DMA interface also has two DMA request clears as inputs (for clearing TX

and RX DMA requests). Each DMA request signal remains asserted until the relevant DMA clear signal is

asserted. After the DMA clear signal is deasserted, a request signal can become active again, if conditions

are setup correctly. The DMA clear signal should be connected to the DMA active signal from the DMA

module. This signal is asserted when DMA is granted access and is active. The DMA active signal is

deasserted when the DMA transfer completes. Connecting the DMA active signal from DMA to the DMA

request clear input of the UART module ensures that no requests are generated by the UART module

while the DMA is active.

The burst transfer and single transfer request signals are not mutually exclusive, and both can be asserted

at the same time. For example, when there is more data than the watermark level in the receive FIFO, the

burst transfer request and the single transfer request are asserted.

The single and burst requests cannot be masked separately by the UART module and if corresponding

DMA (RX or TX) is enabled, both of these requests are sent to the DMA. The DMA configuration selects

either single or burst request as the trigger. All request signals are deasserted if the UART is disabled or

the relevant DMA enable bit (TXDMAE or RXDMAE) in the DMA Control Register [UART_DMACTL] is

cleared.

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SWCU117A–February 2015–Revised March 2015 Universal Asynchronous Receivers and Transmitters (UARTS)

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