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19.4.5 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
through the UART Data [UART_DR] register. Read operations of the [UART_DR] register return a 12-bit
value consisting of 8 data bits and 4 error flags, while write operations place 8-bit data in the TX FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by
setting the FEN bit in the [UART_LCRH] register.
FIFO status can be monitored through the UART Flag [UART_FR] register and the UART Receive Status
[UART_RSR] register. Hardware monitors empty, full, and overrun conditions. The [UART_FR] register
contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the [UART_RSR] register shows
overrun status through the OE bit. If the FIFOs are disabled, the empty and full flags are set according to
the status of the 1-byte-deep holding registers.
The trigger points at which the FIFOs generate interrupts are controlled through the UART Interrupt FIFO
Level Select [UART_IFLS] register. Both FIFOs can be individually configured to trigger interrupts at
different levels. Available configurations include ⅛, ¼, ½, ¾, and ⅞. For example, if the ¼ option is
selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out
of reset, both FIFOs are configured to trigger an interrupt at the ½ mark.
19.4.6 Interrupts
The UART can generate interrupts when the following conditions are observed:
• Overrun error
• Break error
• Parity error
• Framing error
• Receive time-out
• Transmit (when the condition defined in the TXSEL bit in the [UART_IFLS] register is met, or if the
EOT bit in [UART_CTL] is set, when the last bit of all transmitted data leaves the serializer)
• Receive (when the condition defined in the RXSEL bit in the [UART_IFLS] register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can
only generate a single interrupt request to the controller at any given time. Software can service multiple
interrupt events in a single interrupt service routine (ISR) by reading the UART Masked Interrupt Status
[UART_MIS] register.
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask
[UART_IMSC] register by setting the corresponding bits. If interrupts are not used, the raw interrupt status
is always visible through the UART Raw Interrupt Status [UART_RIS] register.
Interrupts can be cleared (for the [UART_MIS] and [UART_RIS] registers) by setting the corresponding bit
in the UART Interrupt Clear [UART_ICR] register.
The receive time-out interrupt is asserted when the RX FIFO is not empty, and no further data is received
over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes empty
through reading all the data (or by reading the holding register), or when the corresponding bit in the
[UART_ICR] register is set.
The UART module provides the possibility of setting and clearing masks for every individual interrupt
source using the UART Interrupt Mask Set/Clear [UART_IMSC] register. The five events that can cause
combined interrupts to CPU are:
• RX: The receive interrupt changes state when one of the following events occurs:
– If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level. When this
happens, the receive interrupt is asserted high. The receive interrupt is cleared by reading data
from the receive FIFO until it becomes less than the trigger level, or by clearing the interrupt.
– If the FIFOs are disabled (have a depth of one location) and data is received, thereby filling the
location, the receive interrupt is asserted high. The receive interrupt is cleared by performing a
single read of the receive FIFO, or by clearing the interrupt.
1332
Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015
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