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2.7.4.3 STCSR Register (Offset = 10h) [reset = X]
STCSR is shown in Figure 2-73 and described in Table 2-99.
SysTick Control and Status This register enables the SysTick features and returns status flags related to
SysTick.
Figure 2-73. STCSR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED COUNTFLAG
R-X R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED CLKSOURCE TICKINT ENABLE
R-X R-1h R/W-X R/W-X
Table 2-99. STCSR Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
16 COUNTFLAG R X
Returns 1 if timer counted to 0 since last time this was read. Clears
on read by application of any part of the SysTick Control and Status
Register. If read by the debugger using the DAP, this bit is cleared
on read-only if the MasterType bit in the **AHB-AP** Control
Register is set to 0. Otherwise, COUNTFLAG is not changed by the
debugger read.
15-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 CLKSOURCE R 1h
Clock source: 0: External reference clock. 1: Core clock External
clock is not available in this device. Writes to this field will be
ignored.
1 TICKINT R/W X
0: Counting down to zero does not pend the SysTick handler.
Software can use COUNTFLAG to determine if the SysTick handler
has ever counted to zero. 1: Counting down to zero pends the
SysTick handler.
0 ENABLE R/W X
Enable SysTick counter 0: Counter disabled 1: Counter operates in a
multi-shot way. That is, counter loads with the Reload value
STRVR.RELOAD and then begins counting down. On reaching 0, it
sets COUNTFLAG to 1 and optionally pends the SysTick handler,
based on TICKINT. It then loads STRVR.RELOAD again, and begins
counting.
133
SWCU117A–February 2015–Revised March 2015
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