User manual

Universal Asynchronous Receiver/Transmitter

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19.1 Universal Asynchronous Receiver/Transmitter

The CC26xx controller includes a UART with the following features:

• Programmable baud-rate generator allowing speeds up to 3 Mbps

• Separate 32 × 8 transmit (TX) and 32 × 12 receive (RX) first-in first-out (FIFO) buffers to reduce CPU

interrupt service loading

• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered

interface

• FIFO trigger levels of ⅛, ¼, ½, ¾, and ⅞

• Standard asynchronous communication bits for start, stop, and parity

• Line-break generation and detection

• Fully programmable serial interface characteristics:

– 5, 6, 7, or 8 data bits

– Even, odd, stick, or no-parity bit generation and detection

– 1 or 2 stop-bit generation

• Support for modem control functions CTS and RTS

• Independent masking of the TX FIFO, RX FIFO RX time-out, modem status, and error conditions

• Standard FIFO-level and end-of-transmission interrupts

• Efficient transfers using micro direct memory access controller (μDMA):

– Separate channels for transmit and receive

– Receive single request asserted when data is in the FIFO; burst request asserted at programmed

FIFO level

– Transmit single request asserted when there is space in the FIFO; burst request asserted at

programmed FIFO level

• Programmable hardware flow control

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Universal Asynchronous Receivers and Transmitters (UARTS) SWCU117A–February 2015–Revised March 2015

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