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www.ti.com Cortex-M3 Processor Registers
2.7.4.1 ICTR Register (Offset = 4h) [reset = X]
ICTR is shown in Figure 2-71 and described in Table 2-97.
Interrupt Control Type Read this register to see the number of interrupt lines that the NVIC supports.
Figure 2-71. ICTR Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED INTLINESNUM
R-X R-1h
Table 2-97. ICTR Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2-0 INTLINESNUM R 1h
Total number of interrupt lines in groups of 32. 0: 0...32 1: 33...64 2:
65...96 3: 97...128 4: 129...160 5: 161...192 6: 193...224 7: 225...256
131
SWCU117A–February 2015–Revised March 2015
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