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Cortex-M3 Processor Registers

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Table 2-96. CPU_SCS Registers (continued)

Offset Acronym Register Name Section

D4Ch ID_AFR0 Auxiliary Feature 0 Section 2.7.4.45

D50h ID_MMFR0 Memory Model Feature 0 Section 2.7.4.46

D54h ID_MMFR1 Memory Model Feature 1 Section 2.7.4.47

D58h ID_MMFR2 Memory Model Feature 2 Section 2.7.4.48

D5Ch ID_MMFR3 Memory Model Feature 3 Section 2.7.4.49

D60h ID_ISAR0 ISA Feature 0 Section 2.7.4.50

D64h ID_ISAR1 ISA Feature 1 Section 2.7.4.51

D68h ID_ISAR2 ISA Feature 2 Section 2.7.4.52

D6Ch ID_ISAR3 ISA Feature 3 Section 2.7.4.53

D70h ID_ISAR4 ISA Feature 4 Section 2.7.4.54

D88h CPACR Coprocessor Access Control Section 2.7.4.55

DF0h DHCSR Debug Halting Control and Status Section 2.7.4.56

DF4h DCRSR Deubg Core Register Selector Section 2.7.4.57

DF8h DCRDR Debug Core Register Data Section 2.7.4.58

DFCh DEMCR Debug Exception and Monitor Control Section 2.7.4.59

F00h STIR Software Trigger Interrupt Section 2.7.4.60

130

SWCU117A–February 2015–Revised March 2015

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