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17.8.7.2 ADCFIFOSTAT Register (Offset = 14h) [reset = X]
ADCFIFOSTAT is shown in Figure 17-66 and described in Table 17-90.
ADC FIFO Status FIFO can hold up to four ADC samples
Figure 17-66. ADCFIFOSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED OVERFLOW UNDERFLOW FULL ALMOST_FULL EMPTY
R-X R-X R-X R-X R-X R-1h
Table 17-90. ADCFIFOSTAT Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
4 OVERFLOW R X
FIFO overflow flag. 0: FIFO has not overflowed. 1: FIFO has
overflowed, this flag is sticky until FIFO is flushed.
3 UNDERFLOW R X
FIFO underflow flag. 0: FIFO has not underflowed 1: FIFO has
underflowed, this flag is sticky until the FIFO is flushed
2 FULL R X
FIFO full flag. 0: FIFO is not full, i.e. there is less than 4 samples in
the FIFO. 1: FIFO is full, i.e. there are 4 samples in the FIFO
1 ALMOST_FULL R X
FIFO almost full flag. 0: There is less than 3 samples in the FIFO, or
the FIFO is full in which case the FULL flag is asserted 1: There are
3 samples in the FIFO, i.e. there is room for one more sample
0 EMPTY R 1h
FIFO empty flag. 0: FIFO contains one or more samples 1: FIFO is
empty
1295
SWCU117A–February 2015–Revised March 2015 AUX – Sensor Controller with Digital and Analog Peripherals
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