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17.8.4.13 JTAGCFG Register (Offset = 40h) [reset = X]
JTAGCFG is shown in Figure 17-48 and described in Table 17-69.
JTAG Configuration This register contains control for configuration of the JTAG domain,- hereunder
access permissions for each TAP.
Figure 17-48. JTAGCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED JTAG_PD_FO
RCE_ON
R-X R/W-1h
7 6 5 4 3 2 1 0
RESERVED
R/W-X
Table 17-69. JTAGCFG Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
8 JTAG_PD_FORCE_ON R/W 1h
Controls JTAG PowerDomain power state: 0: Controlled exclusively
by debug subsystem. (JTAG Powerdomain will be powered off
unless a debugger is attached) 1: JTAG Power Domain is forced on,
independent of debug subsystem. NB: The reset value causes JTAG
Power Domain to be powered on by default. Software must clear this
bit to turn off the JTAG Power Domain
7-0 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1271
SWCU117A–February 2015–Revised March 2015 AUX – Sensor Controller with Digital and Analog Peripherals
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