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AUX – Sensor Controller Registers www.ti.com
17.8.4.3 MCUCFG Register (Offset = 8h) [reset = X]
MCUCFG is shown in Figure 17-38 and described in Table 17-59.
MCU Configuration This register contains power management related bitfields for the MCU domain.
Figure 17-38. MCUCFG Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED VIRT_OFF FIXED_WU_EN
R-X R/W-X R/W-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED SRAM_RET_EN
R-X R/W-Fh
Table 17-59. MCUCFG Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
17 VIRT_OFF R/W X
Internal. Only to be used through TI provided API.
16 FIXED_WU_EN R/W X
Internal. Only to be used through TI provided API.
15-4 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3-0 SRAM_RET_EN R/W Fh
MCU SRAM is partitioned into 4 banks . This register controls which
of the banks that has retention during MCU power off
0h = Retention is disabled
1h = Retention on for SRAM:BANK0
3h = Retention on for SRAM:BANK0 and SRAM:BANK1
7h = Retention on for SRAM:BANK0, SRAM:BANK1 and
SRAM:BANK2
Fh = Retention on for all banks (SRAM:BANK0, SRAM:BANK1
,SRAM:BANK2 and SRAM:BANK3)
1260
AUX – Sensor Controller with Digital and Analog Peripherals SWCU117A–February 2015–Revised March 2015
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