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17.8.3.6 DMACTL Register (Offset = 14h) [reset = X]
DMACTL is shown in Figure 17-25 and described in Table 17-45.
Direct Memory Access Control
Figure 17-25. DMACTL Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED REQ_MODE EN SEL
R-X R/W-X R/W-X R/W-X
Table 17-45. DMACTL Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
2 REQ_MODE R/W X
DMA Request mode
0h = Burst requests are generated on DMA channel 7 when the
condition configured in SEL is met
1h = Single requests are generated on DMA channel 7 when the
condition configured in SEL is met
1 EN R/W X
0: DMA interface is disabled 1: DMA interface is enabled
0 SEL R/W X
Selection of FIFO watermark level required to trigger an ADC_DMA
transfer
0h = ADC_DMA event will be generated when there are valid
samples in the ADC FIFO
1h = ADC_DMA event will be generated when the ADC FIFO is
almost full (3/4 full)
1245
SWCU117A–February 2015–Revised March 2015 AUX – Sensor Controller with Digital and Analog Peripherals
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