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Cortex-M3 Processor Registers
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2.7.3.3 COMP0 Register (Offset = 8h) [reset = X]
COMP0 is shown in Figure 2-63 and described in Table 2-88.
Comparator 0
Figure 2-63. COMP0 Register
31 30 29 28 27 26 25 24
REPLACE RESERVED COMP
R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
COMP
R/W-X
15 14 13 12 11 10 9 8
COMP
R/W-X
7 6 5 4 3 2 1 0
COMP RESERVED ENABLE
R/W-X R/W-X R/W-X
Table 2-88. COMP0 Register Field Descriptions
Bit Field Type Reset Description
31-30 REPLACE R/W X
This selects what happens when the COMP address is matched.
Address remapping only takes place for the 0x0 setting. 0x0: Remap
to remap address. See REMAP.REMAP 0x1: Set BKPT on lower
halfword, upper is unaffected 0x2: Set BKPT on upper halfword,
lower is unaffected 0x3: Set BKPT on both lower and upper
halfwords.
29 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
28-2 COMP R/W X
Comparison address.
1 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 ENABLE R/W X
Compare and remap enable comparator 0. CTRL.ENABLE must also
be set to enable comparisons. 0x0: Compare and remap for
comparator 0 disabled 0x1: Compare and remap for comparator 0
enabled
120
SWCU117A–February 2015–Revised March 2015
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