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Cortex-M3 Processor Registers

2.7.3.2 REMAP Register (Offset = 4h) [reset = X]

REMAP is shown in Figure 2-62 and described in Table 2-87.

Remap This register provides the remap base address location where a matched addresses are

remapped. The three most significant bits and the five least significant bits of the remap base address are

hard-coded to 3'b001 and 5'b00000 respectively. The remap base address must be in system space and

is it required to be 8-word aligned, with one word allocated to each of the eight FPB comparators.

Figure 2-62. REMAP Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED REMAP

R-1h R/W-0h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REMAP RESERVED

R/W-0h R-X

Table 2-87. REMAP Register Field Descriptions

Bit Field Type Reset Description

31-29 RESERVED R 1h

This field always reads 3'b001. Writing to this field is ignored.

28-5 REMAP R/W 0h

Remap base address field.

4-0 RESERVED R X

This field always reads 0. Writing to this field is ignored.

119

SWCU117A–February 2015–Revised March 2015

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