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Watchdog Timer Registers

15.4.1.8 INT_CAUS Register (Offset = 41Ch) [reset = X]

INT_CAUS is shown in Figure 15-9 and described in Table 15-9.

Interrupt Cause Test Mode ITERNAL_NOTE: This register shows the status of Reset and Interrupt when

test mode is enabled, TEST.TEST_EN

Figure 15-9. INT_CAUS Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED CAUSE_RESE CAUSE_INTR

R-X R-X R-X

Table 15-9. INT_CAUS Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1 CAUSE_RESET R X

Indicates that the cause of an interrupt was a reset generated but

blocked due to TEST.TEST_EN (only possible when

TEST.TEST_EN is set).

0 CAUSE_INTR R X

Replica of RIS.WDTRIS

1153

SWCU117A–February 2015–Revised March 2015 Watchdog Timer

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