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www.ti.com Watchdog Timer Registers
15.4.1.6 MIS Register (Offset = 14h) [reset = X]
MIS is shown in Figure 15-7 and described in Table 15-7.
Masked Interrupt Status
Figure 15-7. MIS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED WDTMIS
R-X R-X
Table 15-7. MIS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
0 WDTMIS R X
This register is the masked interrupt status register. The value of this
register is the logical AND of the raw interrupt bit and the WDT
interrupt enable bit CTL.INTEN. Value Description 0: The WDT has
not timed out or is masked. 1: An unmasked WDT time-out event
has occurred.
1151
SWCU117A–February 2015–Revised March 2015 Watchdog Timer
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