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Watchdog Timer Registers

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15.4.1.5 RIS Register (Offset = 10h) [reset = X]

RIS is shown in Figure 15-6 and described in Table 15-6.

Raw Interrupt Status

Figure 15-6. RIS Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED WDTRIS

R-X R-X

Table 15-6. RIS Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 WDTRIS R X

This register is the raw interrupt status register. WDT interrupt

events can be monitored via this register if the controller interrupt is

masked. Value Description 0: The WDT has not timed out 1: A WDT

time-out event has occurred

1150

Watchdog Timer SWCU117A–February 2015–Revised March 2015

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